In order to increase the operating speed of microprocessors, architectures have been designed and implemented that allow for the out-of-order execution of instructions within the microprocessor. An advantage of out-of-order execution of instructions is that it allows load miss latencies to be hidden while useful work is being performed. However, traditionally, load and store instructions have not been executed out of order because of the very nature of their purpose.
Generally, it is architecturally impermissible for a load instruction, which is subsequent in program order to a previous load instruction to return "older" data, which can occur if load instructions are permitted to be executed out of order. Nevertheless, techniques have been implemented to attempt to execute load instructions out of order. However, such techniques have often required too many processor cycles to execute. As microprocessor speeds continually increase, there is a need in the art for an ability to execute in parallel such load instructions and to correct for such problems as described above in a more efficient and faster manner.